1. Field of the Invention
The present invention is related to the field of memory management for personal computers, in particular to a method for performing a fast buffer copy in a personal computer utilizing a paged mode memory architecture and having a cache memory.
2. Description of the Related Art
Personal computer systems are becoming increasingly more powerful, now achieving processing performance levels previously only within the range of minicomputers. Device manufacturers have developed faster and more powerful microprocessors which are rapidly entering the personal computer market. Examples of such microprocessors include Intel Corporation's (Intel) 80386 and 80486 microprocessors. As microprocessors have become increasingly faster, the speed of memory devices is also a major factor in determining the speed that an application will run. While fast memory devices are available, their use in main memory in a computer system is not common due to their high cost.
An alternative to the general use of high speed memory as main memory is to utilize a cache memory system. In a cache memory system, a small amount of fast memory is used as a temporary storage area and slower, more cost effective, memory devices are used in the computer system's main memory. Data contained in portions of the main memory is duplicated in the fast cache memory. An operation requiring data which is stored in the cache memory will be performed at a higher speed than operations which access normal memory. A cache controller is used to determine if the desired information is contained within the cache memory and to control the data transfer from the cache memory. Techniques for the management of cache memory are generally known within the industry. For example, Intel used the cache memory concept when developing the 80386 microprocessor family of devices, including an 82385 cache controller. For detailed information on these devices, please refer to the 1989 Intel Microprocessor and Peripheral Handbook, Volume 1. The use of a cache system generally assures that a copy of the cacheable memory data last read or written by the main processor is maintained in the cache. The amount of information which may be stored in the cache is a function of cache size. There exist a number of algorithms for determining what information will remain in the cache memory. One algorithm is the Least Recently Used (LRU) technique wherein information LRU'd in cache memory is displaced by the next cache miss operation.
Another means of improving speed of memory devices is the use of paged mode dynamic random access memories (DRAM's). A page mode DRAM device may be used in any type of computer system architecture for speeding up main memory access using cheaper RAM. Memory is accessed in a paged memory device by the microprocessor issuing an address for a particular location in the memory array. The address is loaded into a memory controller. The memory controller handles the task of providing the row and column addresses used by a DRAM from the full address provided by the microprocessor. It will be appreciated that placing first the row and then the column address on the DRAM address bus and meeting the particular timing requirements of the DRAM requires a considerable amount of time. The paging technique is used to decrease the amount of time required to access a particular memory address. In a computer system using paged memory DRAM devices, the microprocessor issues a full address to access a specific memory address within a DRAM device as before. However, the memory controller now includes a previous address latch and a comparator to determine if the DRAM row address has changed between successive memory requests. If so, a full row and column address cycle must be issued. However, if the row address has not changed so that the desired memory address is on the same page as the previous access, only a new column address need be provided. It will be appreciated that the time required to access the subsequent memory address is significantly less than that required if the memory controller must issue both a row address and column address and perform a full addressing cycle. If the memory operation is located on the same page, this is known as a page hit. If the row address must be changed because a different page is being requested, this is known as a page miss.
A common operation in computer system applications calls for data stored in a first buffer to be copied to a second buffer. Usually, the two buffers are located on different memory pages. When this situation occurs, the system performance may suffer during the buffer copy operation. For example, if each element of data is to be read from a source buffer located on page P.sub.i and to be written to a target buffer on page P.sub.j on an element-by-element basis, no read or write page hits will occur. The computer system memory controller will read an element from page P.sub.i, write it to page P.sub.j and a page write miss will occur, requiring the issuance of a row and column address, as the memory controller will be required to change pages to perform the write. The memory controller will then read the next element from page P.sub.i and a page read miss will occur as the memory controller must index from page P.sub.j to page P.sub.i. It will be appreciated that each read or write operation will create an associated page miss. These page misses dramatically increase the buffer copy time as compared to a case where page hits occur. Thus, there exists a need for a method to maximize the number of memory page hits during a buffer copy operation.